View FXL4245MPX10_4849445.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 2010 ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator fxl4245 low-voltage, dual-supply, 8-bit, signal translator with configurable voltag e supplies, signal levels, and 3-state outputs features ? bi-directional interface between two levels from 1.1v to 3.6v ? fully configurable, inputs track v cc level ? non-preferential power-up; either v cc may be powered-up first ? outputs remain in 3-state until active v cc level is reached ? outputs switch to 3-state if either v cc is at gnd ? power-off protection ? control inputs (t/r, oe) levels are referenced to v cca voltage ? packaged in 24-pin mlp ? esd protection exceeds: - 4kv human body model (per jesd22-a114 & mil std 883e 3015.7) - 8kv human body model i/o to gnd (per jesd22-a114 & mil std 883e 3015.7) - 1kv charge device model (per esd stm 5.3) - 200v machine model (per jesd22-a115 & esd stm5.2) description the fxl4245 is a configurable dual-voltage-supply translator designed for bi-dir ectional voltage translation of signals between two voltage levels. the device allows translation between voltages as high as 3.6v to as low as 1.1v. the a port tracks the v cca level and the b port tracks the v ccb level. both ports are designed to accept supply voltage levels from 1.1v to 3.6v. this allows for bi-directional voltage translation over a variety of voltage levels: 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. the device remains in 3-state until both v cc s reach active levels, allowing either v cc to be powered-up first. the device also contains power-down control circuits that place the device in 3-state if either v cc is removed. the transmit/receive (t/r) input determines the direction of data flow through the device. the oe input, when high, disables both the a and b ports by placing them in a 3-state condition. the fxl4245 is designed with the control pins (t/r and oe) supplied by v cca . ordering information part number package packing method fxl4245mpx 24-pin molded leadless package (mlp), jedec mo-220, 3.5 x 4.5mm tape and reel
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 2 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator pin configuration figure 1. pin configur ation (top through view) pin definitions pin # name description 1 v cca side-a power supply 2 t/r transmit / receive input 3, 4, 5, 6, 7, 8, 9, 10 a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , a 7 side-a inputs or 3-state outputs 11, 12, 13 gnd ground 14, 15, 16, 17, 18, 19, 20, 21 b 7 , b 6 , b 5 , b 4 , b 3 , b 2 , b 1 , b 0 side-b inputs or 3-state outputs 22 oe output enable input 23, 24 v ccb side-b power supply truth table inputs description oe t/r low voltage level low voltage level bus b data to bus a low voltage level high voltage level bus a data to bus b high voltage level don?t care 3-state
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 3 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter conditions min. max. unit v cca supply voltage -0.5 4.6 v v ccb -0.5 4.6 v i dc input voltage i/o port a -0.5 4.6 v i/o port b -0.5 4.6 control inputs (t/r, oe) -0.5 4.6 v o output voltage (1) output 3-state -0.5 4.6 v output active (a n ) -0.5 to v cca 0.5 output active (b n ) -0.5 to v ccb 0.5 i ik dc input diode current v i < 0v -50 ma i ok dc output diode current v o < 0v -50 ma v o > v cc 50 i oh /i ol dc output source/sink current 50 ma i cc dc v cc or ground current per supply pin 100 ma t stg storage temperature range -65 +150 c esd electrostatic discharge capability human body model, jesd22-a114, mil std 883e 3015.7 4 kv i/o to gnd 8 charged device model, jesd22-c101,stm 5.3 1 machine model, jesd22-a115,stm 5.2 200 v note: 1. i/o absolute maximum ratings must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc power supply operating v cca or v ccb 1.1 3.6 v v i input voltage port a 0 3.6 v port b 0 3.6 control inputs (t/r, oe) 0 v cca i oh /i ol output current v cc0 3.0v to 3.6v 24 ma 2.3v to 2.7v 18 1.65v to 1.95v 6 1.40v to 1.65v 2 1.1v to 1.4v 0.5 t a operating temperature, free air -40 +85 c v/ t minimum input edge rate v cca/b =1.1v to 3.6v 10 ns/v note: 2. all unused inputs must be held at v cci or gnd.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 4 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator electrical characteristics symbol parameter conditions v cci (v) v cco (v) min. max. units v ih high level input (3) data inputs a n , b n 2.70 to 3.60 1.1 to 3.6 2.0 v 2.30 to 2.70 1.6 1.65 to 2.30 0.65 x v cci 1.40 to 1.65 0.65 x v cci 1.10 to 1.40 0.9 x v cci control pins oe, t/r (referenced to v cca ) 2.70 to 3.6 1.1 to 3.6 2.0 2.30 to 2.70 1.6 1.65 to 2.30 0.65 x v cca 1.40 to 1.65 0.65 x v cca 1.10 to 1.40 0.9 x v cca v il low level input (3) data inputs a n , b n 2.70 to 3.60 1.1 to 3.6 0.8 v 2.30 to 2.70 0.7 1.65 to 2.30 0.35 x v cci 1.40 to 1.65 0.35 x v cci 1.10 to 1.40 0.10 x v cci control pins /oe, t/r (referenced to v cca ) 2.70 to 3.60 1.1 to 3.6 0.8 2.30 to 2.70 0.7 1.65 to 2.30 0.35 x v cci 1.40 to 1.65 0.35 x v cci 1.10 to 1.40 0.10 x v cci v oh high level output (4) i oh = -100a 1.1 to 3.6 1.1 to 3.6 v cc0 - 0.2 v i oh = -12ma 2.7 2.7 2.2 i oh = -18ma 3.0 3.0 2.4 i oh = -24ma 3.0 3.0 2.2 i oh = -6ma 2.3 2.3 2.0 i oh = -12ma 2.3 2.3 1.8 i oh = -18ma 2.3 2.3 1.7 i oh = -6ma 1.65 1.65 1.25 i oh = -2ma 1.4 1.4 1.05 i oh = -0.5ma 1.1 1.1 0.75 x v cc0 v ol low level output (4) i ol = 100a 1.1 to 3.6 1.1 to 3.6 0.2 v i ol = 12ma 2.7 2.7 0.4 i ol = 18ma 3.0 3.0 0.4 i ol = 24ma 3.0 3.0 0.55 i ol = 12ma 2.3 2.3 0.4 i ol = 18ma 2.3 2.3 0.6 i ol = 6ma 1.65 1.65 0.3 i ol = 2ma 1.4 1.4 0.35 i ol = 0.5ma 1.1 1.1 0.3 x v cc0 continued on the following page?
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 5 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator electrical characteristics symbol parameter conditions v cci (v) v cco (v) min. max. units i l input leakage current, control pins v i =v cca or gnd 1.1 to 3.6 3.6 1.0 a i off power off leakage current a n , v i or v o =0v to 3.6v 0 3.6 10 a b n , v i or v o =0v to 3.6v 3.6 0 10 i oz 3-state output leakage (0 v o 3.6v, v i =v ih or v il ) a n , b n , /oe=v ih 3.6 3.6 10 a b n , /oe= don?t care (5) 0 3.6 10 a n , /oe= don?t care (5) 3.6 0 10 i cca/b quiescent supply current (6) v i =v cci or gnd; i o =0 1.1 to 3.6 1.1 to 3.6 20 a i ccz 1.1 to 3.6 1.1 to 3.6 20 i cca v i =v cca or gnd; i o =0 0 1.1 to 3.6 -10 1.1 to 3.6 0 10 i ccb v i =v ccb or gnd; i o =0 1.1 to 3.6 0 -10 0 1.1 to 3.6 10 i cca/b increase in i cc per input; other inputs at v cc or gnd v ih =3.0 3.6 3.6 500 a notes: 3. v cci = the v cc associated with the data input under test. 4. v cco = the v cc associated with the output under test. 5. don?t care = any valid logic level. 6. reflects current per supply, v cca or v ccb .
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 6 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator ac electrical characteristics v cca =3.0v to 3.6v symbol parameter t a = -40 to +85c units v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v min. max. min. max. min. max. min. max. min. max. t plh, t phl propagation delay a to b 0.2 3.5 0.3 3.9 0.5 5.4 0.6 6.8 1.4 22.0 ns propagation delay b to a 0.2 3.5 0.2 3.8 0.3 4.0 0.5 4.3 0.8 13.0 t pzh, t pzl output enable /oe to b 0.5 4.0 0.7 4.4 1.0 5.9 1.0 6.4 1.5 17.0 ns output enable /oe to a 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 t phz, t plz output disable /oe to b 0.2 3.8 0.2 4.0 0.7 4.8 1.5 6.2 2.0 17.0 ns output disable /oe to a 0.2 3.7 0.2 3.7 0.2 3.7 0.2 3.7 0.2 3.7 v cca =2.3v to 2.7v symbol parameter t a = -40 to +85c units v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v min. max. min. max. min. max. min. max. min. max. t plh, t phl propagation delay a to b 0.2 3.8 0.4 4.2 0.5 5.6 0.8 6.9 1.4 22.0 ns propagation delay b to a 0.3 3.9 0.4 4.2 0.5 4.5 0.5 4.8 1.0 7.0 t pzh, t pzl output enable /oe to b 0.6 4.2 0.8 4.6 1.0 6.0 1.0 6.8 1.5 17.0 ns output enable /oe to a 0.6 4.5 0.6 4.5 0.6 4.5 0.6 4.5 0.6 4.5 t phz, t plz output disable /oe to b 0.2 4.1 0.2 4.3 0.7 4.8 1.5 6.7 2.0 17.0 ns output disable /oe to a 0.2 4.0 0.2 4.0 0.2 4.0 0.2 4.0 0.2 4.0 v cca =1.65v to 1.95v symbol parameter t a = -40 to +85c units v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v min. max. min. max. min. max. min. max. min. max. t plh, t phl propagation delay a to b 0.3 4.0 0.5 4.5 0.8 5.7 0.9 7.1 1.5 22.0 ns propagation delay b to a 0.5 5.4 0.5 5.6 0.8 5.7 1.0 6.0 1.2 8.0 t pzh, t pzl output enable /oe to b 0.6 5.2 0.8 5.4 1.2 6.9 1.2 7.2 1.5 18.0 ns output enable /oe to a 1.0 6.7 1.0 6.7 1.0 6.7 1.0 6.7 1.0 6.7 t phz, t plz output disable /oe to b 0.2 5.1 0.2 5.2 0.8 5.2 1.5 7.0 2.0 17.0 ns output disable /oe to a 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 7 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator ac electrical characteristics (continued) v cca =1.4v to 1.6v symbol parameter t a = -40 to +85c units v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v min. max. min. max. min. max. min. max. min. max. t plh, t phl propagation delay a to b 0.5 4.3 0.5 4.8 1.0 6.0 1.0 7.3 1.5 22.0 ns propagation delay b to a 0.6 6.8 0.8 6.9 0.9 7.1 1.0 7.3 1.3 9.5 t pzh, t pzl output enable /oe to b 1.1 7.5 1.1 7.6 1.3 7.7 1.4 7.9 2.0 20.0 ns output enable /oe to a 1.0 7.5 1.0 7.5 1.0 7.5 1.0 7.5 1.0 7.5 t phz, t plz output disable /oe to b 0.4 6.1 0.4 6.2 0.9 6.2 1.5 7.5 2.0 18.0 ns output disable /oe to a 1.0 6.0 1.0 6.0 1.0 6.0 1.0 6.0 1.0 6.0 v cca =1.1v to 1.3v symbol parameter t a = -40 to +85c units v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v min. max. min. max. min. max. min. max. min. max. t plh, t phl propagation delay a to b 0.8 13.0 1.0 7.0 1.2 8.0 1.3 9.5 2.0 24.0 ns propagation delay b to a 1.4 22.0 1.4 22.0 1.5 22.0 1.5 22.0 2.0 24.0 t pzh, t pzl output enable /oe to b 1.0 12.0 1.0 9.0 2.0 10.0 2.0 11.0 2.0 24.0 ns output enable /oe to a 2.0 22.0 2.0 22.0 2.0 22.0 2.0 22.0 2.0 22.0 t phz, t plz output disable /oe to b 1.0 15.0 0.7 7.0 1.0 8.0 2.0 10.0 2.0 20.0 ns output disable /oe to a 2.0 15.0 2.0 12.0 2.0 12.0 2.0 12.0 2.0 12.0 capacitance symbol parameter conditions t a =+25c units typical c in input capacitance v cca =v ccb =0v, v i =0v or v cca/b 4 pf c i/o input/output capacitance v cca =v ccb =3.3v, v i =0v or v cca/b 5 pf c pd power dissipation capacitance v cca =v ccb =3.3v, v i =0v or v cc , f=10mhz 20 pf
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 8 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator ac loadings and waveforms figure 2. ac test circuit test switch t plh ,t phl open t plz ,t pzl v cc0 ? 2 at v cco =3.3 0.3v, 2.5v 0.2v, 1.8v 0.15v, 1.5v 0.1v, 1.2v 0.1v t phz ,t pzh gnd table 1. ac load table v cc0 c l r l rtr1 1.2v 0.1v 15pf 2k 2k 1.5v 0.1v 15pf 2k 2k 1.8v 0.15v 30pf 500k 500k 2.5v 0.2v 30pf 500k 500k 3.3v 0.3v 30pf 500k 500k note: 7. input t r =t f =2.0ns, 10% to 90% note: 8. input t r =t f =2.0ns, 10% to 90% figure 3. waveform for inverting and non- inverting functions figure 4. 3-state output low enable and disable for low voltage logic note: 9. input t r =t f =2.0ns, 10% to 90% figure 5. 3-state output high enable and disable for low voltage logic symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v 1.5v 0.1v 1.2v 0.1v v mi v cci /2 v cci /2 v cci /2 v cci /2 v cci /2 v mo v cco /2 v cco /2 v cco /2 v cco /2 v cco /2 v x v oh - 0.3v v oh ? 0.15v v oh ? 0.15v v oh ? 0.1v v oh ? 0.1v v y v ol + 0.3v v ol + 0.15v v ol + 0.15v v ol + 0.1v v ol + 0.1v note : 10. for v mi v cco =v cca for control pins t/r and oe or v cca /2.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 9 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator functional description power-up/power-down sequencing fxl translators offer an advantage in that either v cc may be powered up first. this benefit derives from the chip design. when either v cc is at 0v, outputs are in a high-impedance state. the control inputs (t/r and oe) are designed to track the v cca supply. a pull-up resistor tying oe to v cca should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. the size of the pull-up resistor is based upon the current-sinking capability of the oe driver. the recommended power-up sequence is: 1. apply power to either v cc . 2. apply power to the t/r input (logic high for a-to-b operation; logic low for b-to-a operation) and to the respective data inputs (a port or b port). this may occur at the same time as step 1. 3. apply power to the other v cc . 4. drive the oe input low to enable the device. the recommended power-down sequence is: 1. drive oe input high to disable the device. 2. remove power from either v cc . 3. remove power from the other v cc .
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 10 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator physical dimensions figure 6. 24-pin molded leadless packag e (mlp), jedec mo-220, 3.5 x 4.5mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visit fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/packaging/mlp24b_tnr.pdf .
? 2004 fairchild semiconductor corporation www.fairchildsemi.com fxl4245 ? rev. 1.0.3 11 fxl4245 ? low-voltage, dual-suppl y, 8-bit, signal translator

▲Up To Search▲

Price & Availability of FXL4245MPX10

	To Download FXL4245MPX10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .